ZX9100
The ZX9100 is a next‑gen 32‑bit high‑performance security chip from ZXInfoTek, with built‑in Post‑Quantum Cryptography (PQC) to counter future quantum threats.
The ZX9100 is a next‑gen 32‑bit high‑performance security chip from ZXInfoTek,with built‑in Post‑Quantum Cryptography (PQC) to counter future quantum threats.
Its RISC core offers a 3‑stage pipeline, dual‑issue, FPU, DSP extensions, D/I‑Cache, secure SRAM, PUFSecure‑enhanced OTP, and secure external Flash/PSRAM support. Low‑power hardware crypto engines accelerate PQC algorithms. With rich peripherals and wide temperature/voltage ranges, it serves financial terminals, barcode scanners, PIN pads, secure elements, industrial controls, and consumer MCUs.
CPU characteristics
-RISC-V N310 core, RV32IMAFBCP_Zicsr_Zicond instruction set
-3-stage pipeline, dual-issue, hardware single-precision FPU, DSP extensions (CMSIS-DSP compatible)
-16 KB I-Cache & 16 KB D-Cache, with CCM/PMA support
-PMP (up to 8 entries, 1 KB granularity) for memory access control
-Maximum frequency: 264 MHz
-CoreMark: 2.80 CoreMark/MHz
Memory
-320 KB SRAM (with address scrambling, encryption, and integrity check)
-Dedicated secure SRAM for cryptographic operations
-External SPI Flash (1/2/4-line, transparent encryption, optional 1MB / 2MB / 4MB)
-External PSRAM (2/4/8-line, real‑time encryption, optional 2MB / 4MB)
-8 KB OTP (PUFSecure-enhanced)
-128 Bytes NVRAM (self-destruct on tamper)
Key Peripherals
-Up to 97 GPIO (12 with independent voltage domains)
-USB 2.0 (Host/Device, High-speed/Full-speed, crystal-less support for FS Device)
-Multiple SPI, I2C, UART (with DMA)
Cryptographic Engines
-Symmetric: AES (128/192/256, ECB/CBC/CTR), DES/3DES, SM4 (ECB/CBC/CFB/OFB)
-Hash: SM3, SHA‑0/1/224/256/384/512
-Public-key (PAE): SM2, RSA (up to 4096‑bit), ECC (up to 521‑bit) – with side‑channel protection
Package
-QFN40,QFN88